Several groups of researchers are experimenting and reporting on GaN transistors that are aimed at replacing Si IGBTs (silicon-based insulated-gate bipolar transistors). Advantages of GaN devices are summarized in an article by Boutros, Chu and Hughes, entitled “GaN Power Electronics for Automotive Applications”, (IEEE 2012 Energytech-http://toc.proceedings.com/15872webtoc.pdj). For example, for automotive applications, there is a demand for low-loss power semiconductor switches for high-current/high-voltage electric propulsion units, e.g. 200 A to 600 A and 100 V to 600 V. GaN switches are expected to offer ˜100× performance over silicon-based devices, owing to superior material properties such as high electron mobility and high breakdown field and capability to provide GaN power electronics with low on-resistance and fast switching, and higher operating temperatures (John Roberts, “Lateral GaN Transistors-A Replacement for IGBTs in Automotive Applications”, PCIM Europe 2014; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management; Proceedings of; 20-22 May 2014).
At present, very few high-voltage GaN devices for automotive applications are available on the open marketplace. However, as these devices reach maturity, it is expected that GaN power switches will be introduced into the automotive market for a number of applications such as power generators, power conversion units and electronically controlled on-demand accessories.
For safe operation, normally-off GaN devices with high current and voltage capability are required. Normally-off operation may be provided by series connecting a normally-on GaN transistor with a driver MOSFET in cascode configuration. Alternatively an enhancement mode (E-Mode) normally-on GaN transistor may be used.
A cascode structure can use a conventional MOSFET or a custom structured MOSFET to provide a threshold voltage that approximates to or has an advantage over an IGBT device, e.g. ˜3V and ˜5V for Silicon SJ MOSFETS and Silicon IGBT devices respectively. Alternatively, a normally-off E-Mode GaN transistor can be used. However, E-Mode GaN devices generally have very low threshold voltages, typically 1.5V or less. A low threshold voltage poses a significant problem for safe operation, particularly with respect to noise issues and parasitic elements which could cause voltage spikes or noise in excess of the threshold voltage, thus unintentionally turning on the device. Clearly, unintentional or false switching could be a potential safety hazard for high current and high voltage applications, such as, automotive applications. While it would be desirable to have threshold voltages of 3V or more for high power applications, currently, few vendors offer E-Mode GaN devices with threshold voltages above 2V, and devices with threshold voltages above 3V are rare. Thus, to manage transients caused by noise issues and parasitic elements and ensure safe operation, low threshold voltage E-Mode GaN transistors require carefully designed driver circuitry with signal isolators, isolated +VE and −VE power supplies and a source-sense Kelvin connection.
In addition to considering the potential for noise to cause false switching, another issue for safe operation is the Miller capacitance effect. The latter could result in the power transistor being turned back on when the gate is being taken low.
The use of discrete components and separate driver circuits necessitates interconnection of the components by wire-bonding or other interconnect technologies, which introduces unwanted (parasitic) inductance.
Drivers for cascode GaN devices are disclosed in the above referenced co-pending applications: International Patent Application No. PCT/CA2013/001019 (Publication No. WO2014/094115) entitled “Devices and Systems Comprising Drivers for Power Conversion Circuits”; and U.S. patent application Ser. No. 14/105,569 (Publication No. US 20140175454), entitled “Devices and Systems for Power Conversion Circuits”. These patent applications disclose driver circuits and packaging arrangements for a cascode configuration GaN device, which seek to address one or more issues of thermal management, series inductance and resistance, to reduce or manage unwanted noise and voltage transients, and enable lower cost and more compact systems and devices for electronic power conversion circuits.
For E-Mode GaN devices, which have lower threshold voltages, the use of discrete driver circuitry poses even more significant challenges in managing these issues with noise and parasitic elements, including Miller capacitance effects. Accordingly, there is a need for improved solutions using integrated drivers for E-Mode GaN devices.
Drivers for E-mode GaN devices are disclosed in the above referenced PCT International patent application No. PCT/CA2015/000168 (Publication No. WO2015135072), filed Mar. 10, 2015, entitled “Power Switching Systems Comprising High Power E-Mode GaN Transistors and Driver Circuitry”, which claims priority from U.S. Provisional Patent application No. 61/951,679, filed Mar. 12, 2014 entitled “Power Switching Systems Comprising High Power E-Mode GaN Transistors and Driver Circuitry”. Design guidelines and circuit layer considerations for E-mode drivers are also discussed in more detail, with an example of a particular reference design, in an Application note issued by GaN Systems Inc. (GN001 Rev. 2014-10-21), October 2014, entitled “How to Drive GaN Enhancement Mode Power Switching Transistors”.
Nevertheless, several difficulties associated with driver requirements for E-mode GaN transistors are becoming apparent as the voltage and current handling capability of these GaN transistors continues to improve.
Normally-off or E-mode devices typically have threshold voltages of only 1-2 Volts. This low threshold voltage presents a difficult challenge when external driver devices are used because of the large inductive loop of the extended printed circuit connection tracks that are needed. The inductive elements combine with the distributed and transistor capacitances so that an overshoot voltage plus an extended oscillatory ringing signal is inevitably present.
The Miller Ratio (QGD/QGS) provides an indication of how sensitive a switching transistor is to false, unwanted switching. As the rated voltage increases the GaN transistor Miller Ratio degrades. Thus, higher voltage GaN transistors are more susceptible to false, unwanted—transient operation than low voltage GaN transistors.
The need to overcome these driver difficulties was recognized some years ago, at the time small low voltage GaN transistors were first introduced, for example, as disclosed in a presentation at the Darnell Power Forum, September 2010 by A. Lidow entitled “The GaN Journey Begins” and related references from Efficient Power Corporation.
Although discrete drivers can be used, it is apparent that on-chip drivers offer significant advantages and are likely to become universal in the future. An implementation of a driver circuit based on the above referenced circuit disclosed by Lidow, is illustrated in the circuit schematic of FIG. 1. As shown in FIG. 1, the switching transistor is a small low voltage GaN device D3 that has a pair of GaN transistors D1 and D2 driving its gate electrode to Vcc and ground. The control is therefore transferred and made at the Gate Pad of the integrated driver circuit. The on-chip driver circuitry comprises a pair of series connected GaN transistors D1 and D2. In this configuration, the driver supply voltage Vcc is connected to the drain electrode of D1 while the source electrode of D2 is grounded. The pre-driver circuitry comprises a series of integrated inverter stages to provide a pair of non-overlapping antiphase signals to driver transitions D1 and D2. However, there are drawbacks with this arrangement. The on-chip inductance issue is not addressed and the drive level presented to the large switching transistor D3 is one threshold voltage lower than the supply voltage. In this design, unless the gate drive voltage can be cleanly driven to Vcc, the gate drive voltage may be inadequate to drive D1 effectively.
As disclosed in the above referenced PCT International Patent application No. PCT/CA/2015/000168 (Publication No. WO2015135072), it can be beneficial to provide boost circuitry to provide higher gate drive voltage for the high-side, i.e. pull-up, drive transistor D1. A higher drive voltage, e.g. 10V, is supplied to the gate of D1 to produce firm and rapid pull-up of D1 for improved switching performance at higher switching speeds. Partitioning the driver circuitry enables high current handling components to be integrated closely with the GaN switch and directly coupled, to reduce inductance. Provision of both internal and external source-sense (Kelvin) connections separates the gate loop from the drain-source loop to further reduce the adverse effects of parasitic inductances. A separate pre-driver module or chip, with either discrete or integrated components, allows for the pre-driver to be thermally separated from the GaN chip, e.g. to enable use of lower cost MOSFET pre-drivers.
The following references, and other references cited therein, provide further background information on drivers for GaN FETS:                a) Texas Instruments Inc. Datasheet LM5113 5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETS (SNVS725F—JUNE 2011—REVISED APRIL 2013);        b) U.S. Pat. No. 8,593,211 to Forghani-Sadeh (Texas Instruments Inc.) entitled “System and apparatus for driver circuit for protection of gates of GaN FETS”;        c) U.S. Pat. No. 8,766,711 to Takemae (Transphorm Japan Inc.) entitled “Switching Circuit with Controlled Driver Circuit”.        
In considering the effects of parasitic inductances, it is necessary to consider inductances of on-chip wiring or interconnect, as well as inductances of the interconnection between the chip and the package. It will be apparent that for very large GaN transistors, for example, a device having an area of ˜1 cm2 or more, e.g. a die size of about 10 mm×10 mm, the length of on-chip wiring or interconnect tracks extending between the driver circuitry and electrodes of a large area GaN transistor can also introduce significant parasitic on-chip inductances. For high speed switching, it is desirable to have coherent synchronous turn-on/ turn-off across all elements of a large area GaN transistor. As will be explained in detail more below, with reference to FIG. 3, a very large area GaN transistor may be partitioned into sections, and each section is coupled to the driver circuit by differing lengths of source, drain and gate interconnections. This arrangement, introduces different amounts of parasitic inductance which can result in inductance dependent on the length of interconnect between the driver circuit and the different sections. For fast switching edges, this can lead to out of phase or dissynchronous operation across the different sections of the transistor. Known solutions do not adequately address this issue.
There is a need for further improvements in on-chip drive circuitry, particularly for use with large area, very high voltage, high current, GaN transistors.
The present invention seeks to overcome, or mitigate, one or more of the above-mentioned disadvantages or limitations of these known systems and devices, or at least provide an alternative.